Embodiments of the present invention relate generally to semiconductor chip packaging, and more specifically to a metal pad structure for thickness enhancement of a polymer used in the electrical interconnection of a semiconductor die to a semiconductor chip package substrate with a solder bump.
In a typical assembly of a semiconductor die or integrated circuit to a semiconductor chip package substrate, solder bumps are attached to respective bond pads formed on the die. The semiconductor die is then placed onto the semiconductor chip package substrate. An anneal is performed to join the solder bumps on the semiconductor die to respective bond pads on the semiconductor chip package substrate. Typically, there is a high degree of mismatch between the coefficients of thermal expansion (CTE) between the solder bumps, the semiconductor die and the semiconductor chip package substrate. The mismatch of CTE results in the formation of large strains that cause thermal stresses to develop about the solder bumps and the semiconductor die during thermal cycling. In particular, during the semiconductor die-join cool-down, the solder bumps that are located near the edges and corners of the semiconductor die experience a deformation due to the high degree of mismatch between the CTE between the bumps, the die and the semiconductor chip package substrate. This deformation exerts a rotational force on the bumps at the edges and corners of the semiconductor die, causing them to rotate up and away from their connection with the die. As a result, back-end-of-the-line (BEOL) material that lies underneath the solder bumps in the semiconductor die becomes stressed and may fracture.